Semiconductor device including clock management unit for outputing clock and acknowledgement signals to an intellectual property block

ABSTRACT

A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

CROSS-REFERENCE TO RELATION APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/414,969 filed Jan. 25, 2017 now U.S. Pat. 10,296,065, which claimsthe benefit of U.S. Provisional Patent Application No. 62/286,860 filedon Jan. 25, 2016, U.S. Provisional Patent Application No. 62/286,873filed on Jan. 25, 2016 in the United States Patent and Trademark Office,Korean Patent Application No. 10-2017-0010945 filed on Jan. 24, 2017 inthe Korean Intellectual Property Office, and Korean Patent ApplicationNo. 10-2017-0010943 filed on Jan. 24, 2017 in the Korean IntellectualProperty Office, the disclosures of which are incorporated by referencein their entirety herein.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device.

2. Discussion of Related Art

With the gradual convergence of computers, communication andbroadcasting, the demand for an application specific integrated circuit(ASIC) and an application specific standard product (ASSP) is changingdue to the demand for a system-on-chip (SoC). In addition, the trendtoward lighter, thinner, more compact and higher-performance informationtechnology (IT) devices is one of the factors that drive the developmentof SoCs.

An SoC is a single chip onto which functional blocks (e.g., intellectualproperty (IP) blocks) having various functions are integrated with thehelp of the development of semiconductor processing technology.

As the integration density, size and operation speed of SoCs increase,power consumption becomes more of a design factor. The temperature ofthe SoC may increase when it consumes a large amount of power. If thetemperature increases too greatly, the SoC may malfunction or becomedamaged.

Thus, there is a need for an SoC and methods of driving the SoC that canprevent the SoC from consuming too much power.

SUMMARY

According to an exemplary embodiment of the inventive concept, a systemon chip (SoC) includes a plurality of intellectual property (IP) blocksand a clock management unit (CMU) configured to perform clock gating onat least one of the IP blocks. The IP blocks and the CMU interface withone another using a full handshake method.

According to an exemplary embodiment of the inventive concept, a clockgating component includes a clock control circuit configured to generatean operating clock signal and a channel management (CM) circuitconfigured to receive a request signal across a communication channelfrom an external device, and forward the request signal to the clockcontrol circuit. The clock control circuit is configured to selectivelyprovide the operating clock signal to the external device according tothe request signal and provide an acknowledgement (Ack) signal to the CMcircuit.

According to an exemplary embodiment of the inventive concept, a clockmultiplexer component includes a clock control circuit configured toselect one of a first clock signal and a second clock signal based on afirst selection signal, generate an operating clock signal based on theselected clock signal, and selectively output the operating clock signalin response to a request signal, and a channel management (CM) circuitconfigured to receive the request signal across a communication channelfrom an external device, and forward the request signal to the clockcontrol circuit.

According to an exemplary embodiment of the inventive concept, a clockdividing component includes a clock control circuit configured toperform a dividing operation on an input clock signal to generate adivided clock signal, generate an operating clock signal based on thedivided clock signal, and selectively output the operating clock signalto an external device in response to a request signal, and a channelmanagement (CM) circuit configured to receive the request signal acrossa communication channel from the external device, and forward therequest signal to the clock control circuit.

According to an exemplary embodiment of the inventive concept, a methodof operating a clock management unit (CMU) includes: the CMU determiningwhether a request signal received from an intellectual property (IP)block indicates the IP block desires to enter a selected one of anactive mode and a sleep mode; the CMU outputting an acknowledgement(Ack) signal at an activated level and a clock signal to the IP blockwhen the request signal indicates the IP block desires to enter theactive mode; and the CMU outputting the Ack signal at a deactivatedlevel to the IP block and stopping output of the clock signal to the IPblock when the clock request signal indicates the IP block desires toenter the sleep mode.

According to an exemplary embodiment of the inventive concept, a clockmanagement unit (CMU) includes a controller circuit configured to outputa first clock signal based on an output from a phase locked loop or anoscillator, a multiplexing circuit configured to output one of the firstclock signal and a second clock signal, a first clock dividing circuitconfigured to perform a first dividing operation on an output of themultiplexing circuit to generate a third clock signal, a shortstopcircuit configured to selectively stop pulses of the third clock signalto generate a fourth clock signal, a second clock dividing circuitconfigured to perform a second dividing operation on an output of theshortstop circuit to generate a fifth clock signal, and a first clockgating circuit configured to selectively output the fifth clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concept will become apparent and more readily appreciatedfrom the following description of the exemplary embodiments thereof,taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept;

FIG. 2 is a block diagram of a clock management unit (CMU) included in asemiconductor device according to an exemplary embodiment of the presentinventive concept;

FIG. 3 is a block diagram of an intellectual property (IP) blockincluded in a semiconductor device according to an embodiment of thepresent inventive concept;

FIG. 4 illustrates signal transmission paths between a plurality ofclock control circuits of a CMU according to an exemplary embodiment ofthe present inventive concept;

FIG. 5A illustrates a clock request signal and a clock acknowledgementsignal that may be used in a CMU according to an exemplary embodiment ofthe present inventive concept;

FIG. 5B illustrates clock level transitions for the clock request signaland the clock acknowledgement signal that may occur in a CMU accordingto an exemplary embodiment of the present inventive concept;

FIG. 6 illustrates the implementation of a clock gating componentincluded in a semiconductor device according to an exemplary embodimentof the present inventive concept;

FIG. 7 illustrates the structure of the clock gating component includedin a semiconductor device according to an exemplary embodiment of thepresent inventive concept;

FIG. 8 is a timing diagram illustrating a behavior of the clock gatingcomponent included in a semiconductor device according to an exemplaryembodiment of the present inventive concept;

FIG. 9A illustrates the implementation of a clock multiplexer (MUX)component included in a semiconductor device according to an exemplaryembodiment of the present inventive concept;

FIG. 9B illustrates a finite state machine (FSM) of the clock MUXcomponent included in a semiconductor device according to an exemplaryembodiment of the present inventive concept;

FIG. 10 illustrates the structure of the clock MUX component included ina semiconductor device according to an exemplary embodiment of thepresent inventive concept;

FIGS. 11 through 20 are timing diagrams illustrating the behavior of theclock MUX component included in a semiconductor device according to anexemplary embodiment of the present inventive concept;

FIG. 21A illustrates a clock dividing component included in asemiconductor device according to an exemplary embodiment of the presentinventive concept;

FIG. 21B illustrates an FSM of the clock dividing component included ina semiconductor device according to an exemplary embodiment of thepresent inventive concept;

FIG. 22 illustrates a clock dividing component included in asemiconductor device according to an exemplary embodiment of the presentinventive concept;

FIG. 23 is a timing diagram illustrating the behavior of the clockdividing component included in a semiconductor device according to anembodiment of the present inventive concept;

FIG. 24 illustrates a phase locked loop (PLL) controller included in asemiconductor device according to an exemplary embodiment of the presentinventive concept;

FIG. 25 illustrates a multiplexer of the PLL controller circuit includedin a semiconductor device according to an exemplary embodiment of thepresent inventive concept;

FIGS. 26 and 27 are timing diagrams illustrating a behavior of the PLLcontroller included in a semiconductor device according to an exemplaryembodiment of the present inventive concept;

FIG. 28 illustrates a PLL user controller included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIG. 29 illustrates an adapter component included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIG. 30 illustrates the structure of a hysteresis filter included in asemiconductor device according to an exemplary embodiment of the presentinventive concept;

FIGS. 31 through 33 are timing diagrams illustrating a behavior of thehysteresis filter included in a semiconductor device according to anexemplary embodiment of the present inventive concept;

FIG. 34 is a block diagram of a power management unit (PMU) included ina semiconductor device according to an exemplary embodiment of thepresent inventive concept;

FIGS. 35 through 39 are timing diagrams illustrating examples of a clockon/off operation of the PMU; and

FIG. 40 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 1, the semiconductor device according to an exemplaryembodiment of the present inventive concept includes an input/output(I/O) pad 101, a clock management unit (CMU) 100, a power managementunit (PMU) 300, and a logic block (e.g., one or more logic circuits).For example, the logic block may be implemented as one or moreintellectual property (IP) blocks 200 through 220. In an embodiment, anIP block is an IP core or reusable unit of logic or chip layout that isthe intellectual property of one party. In an embodiment, thesemiconductor device is or includes a system-on-chip (SoC).

The CMU 100 generates an operation (or operating) clock signal that isto be provided to each of the first through third IP blocks 200 through220. For example, the CMU 100 may generate first through third clocksignals CLK1 through CLK3.

The first through third IP blocks 200 through 220 may be connected to asystem bus and communicate with each other through the system bus. In anembodiment, each of the first through third IP blocks 200 through 220include a processor, a graphic processor, a memory controller, an inputand output interface block, etc.

The CMU 100 may provide the first clock signal CLK1 to the first IPblock 200. The CMU 100 may provide the second clock signal CLK2 to thesecond IP block 210. The CMU 100 may provide the third clock signal CLK3to the third IP block 220.

Any one of the first through third IP blocks 200 through 220 maytransmit a clock request signal to the CMU 100 according to a fullhandshake method (e.g., a synchronous handshake). The clock requestsignal may indicate that the corresponding IP block desires for the CMU100 to provide it with a clock signal or desires for the CMU 100 to stopproviding it with the clock signal. In an embodiment, in a fullhandshake method, the CMU 100 responds to the clock request signal witha clock acknowledgement signal indicating it is currently providing oris about to provide the requested clock signal, or it has stoppedproviding or is about to stop providing the requested clock signal. Inan embodiment, the CMU 100 respond with a clock acknowledgement signalindicating only that it is acknowledging receipt of the clock requestsignal without providing information on the state of the clock signal.

For example, the first IP block 200 may transmit a first clock requestsignal REQ1 to the CMU 100 according to the full handshake method. TheCMU 100 may transmit a first clock acknowledgement signal ACK1 to thefirst IP block 200 in response to receipt of the first clock requestsignal REQ1. At the same time or prior to transmitting the first clockacknowledgement signal ACK1, the CMU 100 may transmit the first clocksignal CLK1 to the first IP block 200.

In an embodiment, an interface between the CMU 100 and the first throughthird IP blocks 200 through 220 has the format of the full handshakemethod. In an embodiment, the interface may be implemented to follow,but not limited to, a Low Power Interface (LPI), a Q-Channel Interfaceor a P-Channel Interface of ARM Ltd.

Clock gating may be used to divide a computer system into smallfunctional blocks and then cut off power supply to unused parts. Sincenot all parts of the computer system are always in operation, blocks inunused parts may be stopped to reduce power consumption and generationof heat in the stopped blocks.

The CMU 100 according to an exemplary embodiment of the inventiveconcept performs clock gating on some of the first through third IPblocks 200 through 220 which do not require operation clock signals. TheCMU 100 can reduce power consumption by automatically performing clockgating without creating errors in IP block operation.

The PMU 300 controls a power supply to the semiconductor device. Forexample, when the semiconductor device enters a standby mode, the PMU300 cuts off power supply to the SoC by turning off a power controlcircuit. Here, the PMU 300 continuously consumes power. However, sincethe power consumed by the PMU 300 is far smaller than that consumed bythe entire semiconductor device, the power consumption of thesemiconductor device is significantly reduced in the standby mode.

Specifically, when the SoC is in the standby mode, the PMU 300 may cutoff power supply to the CMU 100. This may correspond to a case wherethere is no clock request from the first through third IP blocks 200through 220. For example, the PMU 300 may cut off power supply to theCMU 100 if none of the IP blocks have made a request for a clock signalwithin a pre-defined period of time.

FIG. 2 is a block diagram of the CMU 100 included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 2, the CMU 100 includes clock components 120 a through120 g (e.g., clock gating circuits), channel management circuits (CM)130 and 132, and a CMU controller 110. The clock components 120 athrough 120 g are configured to generate clock signals that are to beprovided to the IP blocks 200 and 210, and the channel managementcircuits 130 and 132 are disposed between the clock components 120 f and120 g and the IP blocks 200 and 210 to provide communication channels CHbetween the CMU 100 and the IP blocks 200 and 210. The CMU controller110 provides clock signals to the IP blocks 200 and 210 using the clockcomponents 120 a through 120 g. In an alternate embodiment, the channelmanagement circuits 130 and 132 are omitted and the last clockcomponent(s) provide communication channels CH between the CMU 100 andthe IP blocks 200 and 210.

In some embodiments, the communication channels CH provided by thechannel management circuits 130 and 132 may be implemented to follow,but not limited to, LPI, Q-Channel Interface or P-Channel Interface ofARM Ltd. The communication channels CH can also be implemented to followa different communication protocol.

The clock components 120 a through 120 g include clock sources (CS) 124a through 124 g (e.g., clock signal generators) and clock controlcircuits (CC) 122 a through 122 g which control the clock sources 124 athrough 124 g, respectively. The clock sources 124 a through 124 g mayinclude, for example, a multiplexer (MUX) circuit, a clock dividingcircuit, a shortstop circuit, and a clock gating circuit.

The clock components 120 a through 120 g form a parent-childrelationship with each other. In the current embodiment, the clockcomponent 120 a is a parent of the clock component 120 b, and the clockcomponent 120 b is a child of the clock component 120 a and a parent ofthe clock component 120 c. In addition, the clock component 120 e is aparent of two clock components 120 f and 120 g, and the clock components120 f and 120 g are children of the clock component 120 e. In thecurrent embodiment, the clock component 120 a located closest to a phaselocked loop (PLL) is referred to as a root clock component, and theclock components 120 f and 120 g located closest to the IP blocks 200and 210 may be referred to as leaf clock components. The parent-childrelationship is also, inevitably, formed between the clock controlcircuits 122 a through 122 g and between the clock sources 124 a through124 g according to the parent-child relationship between the clockcomponents 120 a through 120 g.

The clock control circuits 122 a through 122 g exchange a clock requestREQ and an acknowledgement ACK for the clock request REQ between aparent and a child and provide clock signals to the IP blocks 200 and210.

If the IP block 200 does not need a clock signal, for example, if the IPblock 200 needs to be in a sleep state, the CMU 100 stops providing theclock signal to the IP block 200.

Specifically, the channel management circuit 130 transmits to the IPblock 200 a first signal indicating that it will stop providing a clocksignal under the control of the CMU 100 or the CMU controller 110. TheIP block 200 which receives the first signal transmits to the channelmanagement circuit 130 a second signal indicating that the provision ofthe clock signal can be stopped after the completion of an operationbeing processed. The channel management circuit 130 which receives thesecond signal from the IP block 200 requests the clock component 120 f,i.e., its parent to stop providing the clock signal.

In an example, if the communication channel CH provided by the channelmanagement circuit 130 follows Q-Channel Interface, the channelmanagement circuit 130 transmits a QREQn signal having a first logicvalue (e.g., logic low, hereinafter indicated by reference character“L”) to the IP block 200 as the first signal. Then, when receiving aQACCEPTn signal having the first logic value from the IP block 200 asthe second signal, the channel management circuit 130 transmits a clockrequest REQ (e.g., a signal) having the first logic value to the clockcomponent 120 f. In this case, the clock request REQ having the firstlogic value is a “clock provision stop request.”

The clock control circuit 122 f which receives the clock request REQ(i.e., the clock provision stop request) having the first logic valuefrom the channel management circuit 130 stops providing a clock signalby disabling the clock source 124 f. For example, the clock controlcircuit 122 f can disable the clock source 124 f by providing a disablesignal to the clock source 124 f. Accordingly, the IP block 200 canenter a sleep mode. In this process, the clock control circuit 122 f mayprovide an acknowledgement ACK having the first logic value to thechannel management circuit 130. However, it should be noted that even ifthe channel management circuit 130 receives the acknowledgement ACKhaving the first logic value after transmitting the clock provision stoprequest having the first logic value, it may not guarantee the stoppageof clock provision by the clock source 124 f. In an embodiment, theacknowledgement ACK merely means the clock control circuit 122 f isaware of the fact that the clock component 120 f (i.e., a parent of thechannel management circuit 130) no longer needs to provide a clocksignal to the channel management circuit 130.

Meanwhile, the clock control circuit 122 f of the clock component 120 ftransmits a clock request REQ having the first logic value to the clockcontrol circuit 122 e of the clock component 120 e which is its parent.If the IP block 210 also does not need a clock signal, for example, ifthe clock control circuit 122 e receives the clock provision stoprequest from the clock control circuit 122 g, the clock control circuit122 e stops providing the clock signal by disabling the clock source 124e (e.g., the clock dividing circuit). Accordingly, the IP blocks 200 and210 can enter the sleep mode.

The above operation may be performed in the same way for other clockcontrol circuits 122 a through 122 d.

Although the clock control circuit 122 f of the clock component 120 ftransmits the clock request REQ having the first logic value to theclock control circuit 122 e of the clock component 120 e which is itsparent, if the IP block 210 is running, the clock control circuit 122 ecannot disable the clock source 124 e. Only when the IP block 210 nolonger needs a clock signal, can the clock control circuit 122 e disablethe clock source 124 e and transmit a clock request REQ having the firstlogic value to the clock control circuit 120 d which is its parent. Thatis, the clock control circuit 122 e can disable the clock source 124 eonly when receiving the clock provision stop request from both of theclock control circuits 122 f and 122 g.

When the IP blocks 200 and 210 are in the sleep state, all of the clocksources 124 a through 124 f may be disabled. Then, when the IP block 200enters the running state, the CMU 100 resumes providing clock signals tothe IP blocks 200 and 210.

The channel management circuit 130 transmits a clock request REQ havinga second logic value (e.g., logic high, hereinafter indicated byreference character “H”) to the clock control circuit 122 f of the clockcomponent 120 f which is its parent and waits for an acknowledgement ACKfrom the clock control circuit 122 f. Here, the clock request REQ havingthe second logic value is a “clock provision request,” and theacknowledgement ACK for the clock provision request indicates that clockprovision by the clock source 124 f has been resumed. The clock controlcircuit 122 f cannot immediately enable the clock source 124 f (e.g.,the clock gating circuit) but waits for the provision of a clock signalby its parent.

Then, the clock control circuit 122 f transmits a clock request REQ(i.e., the clock provision request) having the second logic value to theclock control circuit 122 e which is its parent and waits for anacknowledgement ACK from the clock control circuit 122 e. This operationmay be performed in the same way for the clock control circuits 122 athrough 122 d. For example, each clock control circuit in the cascadeexcept the first sends a clock provision request to its parent.

The first clock control circuit 122 a (i.e. the root clock component),which receives a clock request REQ having the second logic value fromthe clock control circuit 122 b enables the first clock source 124 a(e.g., the MUX circuit) and transmits an acknowledgement ACK to thesecond clock control circuit 122 b. The second clock control circuit 122b enables the second clock source 124 b in response to receipt of theACK from the first clock control circuit 122 a, and transmits an ACK tothe third clock control circuit 122 c. The process repeats with thethird, fourth, and fifth clock control circuits 122 c-122 e. After theclock sources 124 b through 124 e are enabled sequentially in this way,the fifth clock control circuit 122 e finally transmits to a first leafclock control circuit 122 f an acknowledgement ACK notifying the leafclock control circuit that the clock provision by the clock source 124 ehas been resumed. The first leaf clock control circuit 122 f whichreceives the acknowledgement ACK provides a clock signal to the IP block200 by enabling the clock source 124 f and provides an acknowledgementACK to the channel management circuit 130.

As described above, the clock control circuits 122 a through 122 goperate according to the full handshake method (e.g., synchronoushandshaking) in which a clock request REQ and an acknowledgement ACK forthe clock request REQ are exchanged between a parent and a child.Accordingly, the clock control circuits 122 a through 122 g can controlclock signals provided to the IP blocks 200 and 210 by controlling theclock sources 124 a through 124 g hardware-wise.

The clock control circuits 122 a through 122 g may transmit a clockrequest REQ to their parents or control the clock sources 124 a through124 g by operating on their own or under the control of the CMUcontroller 110. In some embodiments, the clock control circuits 122 athrough 122 g may respectively include finite state machines (FSMs)which control the clock sources 124 a through 124 g according to a clockrequest REQ exchanged between a parent and a child.

While FIG. 2 shows a tree of clock components including a cascade offive clock components and two leaf clock components, the inventiveconcept is not limited thereto. In alternative embodiments, one or moreof these clock components may be omitted. In a first embodiment, onlythe first clock component 120 a and the first leaf clock component 120 fare present, the second-fifth clock components 120 b-120 e are omitted,and the second leaf clock component 120 g is omitted. In a secondembodiment, only the second clock component 120 b and the first leafclock component 120 f are present, the first clock component 120 a isomitted, the third-fifth clock components 120 c-120 e are omitted, andthe second leaf clock component 120 g is omitted. In a third embodiment,only the third clock component 120 c and the first leaf clock component120 f are present, the first-second clock components 120 a-b areomitted, the fourth-fifth clock components 120 d-e are omitted, and thesecond leaf clock component 120 g is omitted. In a fourth embodiment,only the fourth clock component 120 d and the first leaf clock component120 f are present, the first-third clock components 120 a-c are omitted,the fifth clock component 120 e is omitted, and the second leafcomponent 120 g is omitted. In a fifth embodiment, only the fifth clockcomponent 120 e and the first leaf clock component 120 f are present,the first-fourth clock components 120 a-120 d are omitted, and thesecond leaf clock component 120 g is omitted. These embodiments may bevaried further with various other combinations. For example, in a sixthembodiment, the first-second clock components 120 a-120 b are present,the first leaf clock component clock 120 f is present, the third-fifthclock components 120 b-e are omitted, and the second leaf clockcomponent 120 g is omitted.

In an exemplary embodiment, the first clock component 120 a is aphase-locked loop (PLL) controller.

In an exemplary embodiment, the PLL controller receives from anoscillator OSC a constant or variable frequency signal oscillated by theoscillator OSC and PLL signal by a PLL, and outputs one of the tworeceived signals based on a certain condition. When the components needthe PLL signal, the PLL controller outputs the PLL signal. When thecomponents need the oscillator signal, the PLL controller outputs theoscillator signal. When a component using an output of the PLL is notpresent, in an embodiment of the inventive concept, the PLL controllerturns off the PLL. In an alternate embodiment, when the component usingthe output of the PLL is not present, the PLL controller automaticallycontrols the PLL to enter a bypass mode. In another alternateembodiment, when the component using the output of the PLL is notpresent, the PLL controller does not affect the operation of the PLL atall.

The PLL controller can be replaced by any component that generates clocksignals. For example, the PLL controller can be implemented using a ringoscillator or a crystal oscillator.

In an exemplary embodiment of the inventive concept, the clock component120 b is a clock multiplexer (MUX) unit.

In an embodiment, the clock MUX unit includes the clock control circuit122 b and the MUX circuit 124 b. The clock control circuit 122 b of theclock MUX unit may operate with a sequential behavior. The clock controlcircuit 122 b may control the turning on or off of a clock signal. Tochange the MUX selection of the clock MUX unit in a state where theclock signal is off, the clock control circuit 122 b generates a clockrequest signal. The clock request signal generated by the clock controlcircuit 122 b to change the MUX selection may be provided only to aprevious parent clock component and a next parent clock component or maybe provided to all possible parent clock components. In an alternativeembodiment, the clock control circuit 122 b does not generate the clockrequest signal to change the MUX selection in a state where the clocksignal is off. For example, in this embodiment, the clock controlcircuit 122 b only changes the MUX selection when the clock signal isalready on.

The clock control circuit 122 b of the clock MUX unit may transmit theclock request signal only to a parent clock component that is used. Theclock MUX unit may have two or more input clock signals. For example,FIG. 2 shows the MUX circuit 124 b receiving a first clock signal CLK1output from the first clock control circuit 124 a and a second clocksignal CLK2, which may be received from an external CMU or otherexternal device. The MUX circuit 124 b can then select one of the firstand second clock signals CLK1 and CLK2 for output based on a certaincondition.

In an exemplary embodiment of the inventive concept, the clock component120 c is a clock dividing unit such as a clock divider circuit (e.g., afrequency dividing circuit). The clock divider circuit takes an inputsignal of an input frequency and generates an output signal with anoutput frequency of the input frequency divided by a clock dividingratio. For example, the dividing ratio may be an integer greater than 1.

In an embodiment, the clock dividing unit includes the clock controlcircuit 122 c and a dividing circuit 124 c. The clock control circuit122 c of the clock dividing unit may operate with a sequential behavior.The clock control circuit 122 c may control the turning on or off of aclock signal output by the dividing circuit 124 c. To change the clockdividing ratio of the dividing circuit 124 c in a state where the clocksignal is off, the clock control circuit 122 c may generate a clockrequest signal. For example, the clock control circuit 122 c may outputa clock request signal to a root clock component that causes thedividing circuit 124 c to begin receiving a clock signal so it canperform a dividing operation on the received clock signal. In analternate embodiment, the clock control circuit 122 c does not generatethe clock request signal to change the clock dividing ratio of thedividing circuit 124 c in the state where the clock signal is off. Forexample, in this embodiment, the clock control circuit 122 c onlychanges the clock dividing ratio when the clock signal is already on.

In an exemplary embodiment, the clock component 120 d is a shortstopunit. In an embodiment, the shortstop unit provides a clock signal witha plurality of pulses during a first period, stops these pulses during asecond period after the first period, and resumes the pulses duringthird period after the second period.

The shortstop unit includes the clock control circuit 122 d and theclock gating circuit 124 d. In an embodiment, the clock gating circuit124 d selectively outputs a clock signal based on a certain condition.The clock control circuit 122 d of the shortstop unit may operate with asequential behavior. The clock control circuit 122 d may control turningon or off of a clock signal. When a clock request signal from a childclock component is inactive, the clock control circuit 122 d mayactivate the clock gating circuit 124 d. For example, even though theclock control circuit 122 d has been notified to stop provisioning aclock signal by a child clock component, the clock control circuit 122 dmay activate the clock gate circuit 124 d when a certain conditionoccurs.

In an exemplary embodiment of the inventive concept, each of the leafclock components 120 f and 120 g is a clock gating unit. In anembodiment where the leaf clock components 120 f and 120 g are clockgating units, each component includes a clock gate circuit.

The clock gating unit may communicate with at least one of the channelmanagement circuits 130 and 132 according to the full handshake method.

Referring to FIGS. 1 and 2, in an exemplary embodiment of the inventiveconcept, the PMU 300 transmits a power control signal to the oscillatorOSC in response to a wake-up signal received in a standby mode. Theoscillator OSC is an oscillation circuit which generates a certainfrequency signal and supplies an operation clock signal to a logic block(e.g., clock component 120 a). A crystal oscillator generates a signalwith an accurate and stable oscillation frequency using piezoelectricoscillation of a crystal XTAL.

When power is input to the oscillator OSC, the oscillator OSC begins tooscillate. The oscillator OSC initially outputs a fine and unstablesignal and then gradually begins to output a stable oscillation clocksignal. The CMU 100 may supply an operation clock signal to the logicblock after the oscillation clock signal output from the oscillator OSCis stabilized.

FIG. 3 is a block diagram of an IP block included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 3, the first IP block 200 includes a channel adapter202 and an IP core 204. In FIG. 3, the first IP block 200 is illustratedas an example. However, the second and third IP blocks 210 and 220 mayinclude substantially the same elements as the first IP block 200.

In an embodiment, the channel adapter 202 communicates with the firstchannel management circuit 130 according to the full handshake method.Through the channel adapter 202, the first IP block 200 can transmit thefirst clock request signal REQ1 and receive the first clock signal CLK1.For example, the first IP block 200 may transmit REQ1 to the firstchannel management circuit 130 and receive the clock signal CLK outputby leaf clock component 120 f as CLK1 in response to transmitting REQ1.Alternatively, through the channel adapter 202, the first IP block 200can transmit the first clock request signal REQ1, receive anacknowledgement signal indicating the presence of a clock signal, andreceive the first clock signal CLK1 directly from a clock componentcontrolled by the channel adapter 202.

The IP core 204 may include, for example, a processor, a graphicprocessor, a memory controller, an input and output interface block,etc.

FIG. 4 illustrates signal transmission paths between a plurality ofclock control circuits.

Referring to FIG. 4, the clock control circuits may operate using ahandshake signal including a clock request signal REQ and anacknowledgement (or a clock acknowledgement signal) ACK which is aresponse signal to the clock request signal REQ. The clock requestsignal REQ and the clock acknowledgement signal ACK may have, e.g., thefirst logic value (e.g., logic low) or the second logic value (e.g.,logic high). However, the clock request signal REQ and the clockacknowledgement signal ACK can also be implemented in other ways.

In an exemplary embodiment of the inventive concept, a clock consumertransmits the clock request signal REQ having the second logic value toa clock provider, thereby informing the clock provider that a clocksignal is needed. Conversely, the clock consumer may transmit the clockrequest signal REQ having the first logic value to the clock provider,thereby informing the clock provider that the clock signal is no longerneeded.

Meanwhile, the clock provider may transmit the clock acknowledgementsignal ACK having the second logic value to the clock consumer. Theclock acknowledgement signal ACK having the second logic value indicatesthat a clock signal is being stably provided to the clock consumer bythe clock provider. Conversely, the clock provider may transmit theclock acknowledgement signal ACK having the first logic value to theclock consumer. In an embodiment, the clock acknowledgement signal ACKhaving the first logic value indicates that the clock provider cannotinform the clock consumer about the provision of the clock signal. Forexample, the clock provider providing the ACK having the first logiclevel may indicate that the clock provider is merely aware of the clockconsumer's desire for a clock signal and unable to notify the clockconsumer when the clock signal is being stable provided.

In an example, the clock control circuit 122 b, as a clock consumer, maytransmit, e.g., a clock request signal PARENT_CLK_REQ having the secondlogic value to the clock control circuit 122 a which is a clockprovider, thereby informing the clock control circuit 122 a that a clocksignal is needed. Accordingly, a clock component (i.e., a clockprovider) including the clock control circuit 122 a may transmit a clocksignal to a clock component (i.e., a clock consumer) including the clockcontrol circuit 122 b. Then, the clock control circuit 122 b mayreceive, e.g., a clock acknowledgement signal PARENT_CLK_ACK having thesecond logic value from the clock control circuit 122 a.

Meanwhile, the clock control circuit 122 b, as a clock provider, mayreceive, e.g., a clock request signal CHILD_CLK_REQ having the secondlogic value from the clock control circuit 122 f. Through the receptionof the clock request signal CHILD_CLK_REQ having the second logic value,the clock control circuit 122 b may become aware that the clock controlcircuit 122 f which is a clock consumer needs a clock signal.Accordingly, the clock component (i.e., a clock provider) including theclock control circuit 122 b may provide a clock signal to a clockcomponent (i.e., a clock consumer) including the clock control circuit122 f. Then, the clock control circuit 122 b, as a clock provider, maytransmit, e.g., a clock acknowledgement signal CHILD_CLK_ACK having thesecond logic value to the clock control circuit 122 f.

In another example, the clock control circuit 122 b, as a clockconsumer, may transmit, e.g., the clock request signal PARENT_CLK_REQhaving the first logic value to the clock control circuit 122 a which isa clock provider, thereby informing the clock control circuit 122 a thata clock signal is no longer needed. Accordingly, the clock controlcircuit 122 b may receive, e.g., the clock acknowledgement signalPARENT_CLK_ACK having the first logic value from the clock controlcircuit 122 a. The clock acknowledgement signal PARENT_CLK_ACK havingthe first logic value indicates that clock provision by the clockprovider is not guaranteed.

Meanwhile, the clock control circuit 122 b, as a clock provider, mayreceive, e.g., the clock request signal CHILD_CLK_REQ having the firstlogic value from the clock control circuit 122 f. The clock requestsignal CHILD_CLK_REQ having the first logic value indicates that theclock control circuit 122 f which is a clock consumer no longer needs aclock signal. Accordingly, the clock control circuit 122 b may transmit,e.g., the clock acknowledgement signal CHILD_CLK_ACK having the secondlogic value to the clock control circuit 122 f. The clockacknowledgement signal CHILD_CLK_ACK having the second logic valueindicates that the clock provision by the clock provider is notguaranteed.

It should be noted that a combinational path between these clock controlcircuits may include a first path (e.g., a first wire or communicationchannel) through which the clock control circuit 122 b transmits theclock request signal PARENT_CLK_REQ to the clock control circuit 122 awhich is its parent and then receives the clock acknowledgement signalPARENT_CLK_ACK from the clock control circuit 122 a which is its parentand a second path (e.g., a second wire or communication channel) throughwhich the clock control circuit 122 b receives the clock request signalCHILD_CLK_REQ from the clock control circuit 122 f which is its childand then transmits the clock acknowledgement signal CHILD_CLK_ACK to theclock control circuit 122 f which is its child but that thecombinational path does not include a path (indicated by referencecharacter ‘X’ in FIG. 4). For example, if the path X were present, theclock acknowledgement signal PARENT_CLK_ACK received from the clockcontrol circuit 122 a could pass through the path X or the clock requestsignal PARENT_CLK_REQ could pass through path X.

The clock request signal REQ and the clock acknowledgement signal ACKare implemented according to the full handshake method, and a clockprovider and a clock consumer may belong to a single clock domain or todifferent clock domains. When a clock provider and a clock consumerbelong to a single clock domain, they operate in response to a samereference clock signal. When a clock provider and a clock consumerbelong to different clock domains, they operate in response to differentreference clock signals.

In an exemplary embodiment, the clock MUX circuit, the clock dividingcircuit, the clock gating circuit, etc. connected respectively to theclock control circuits for communication use different clock domainsfrom the clock control circuits. That is, a clock frequency in a signalline which transmits a clock request signal may be different from aclock frequency of an operation clock signal actually provided.

FIG. 5A illustrates a clock request signal REQ and a clockacknowledgement signal ACK used herein. FIG. 5B illustrates clock leveltransitions for the clock request signal REQ and the clockacknowledgement signal ACK used herein.

Referring to FIG. 5A, the clock request signal REQ transits to thesecond logic value at a time T1. This may indicate that a clock consumerinforms a clock provider that the clock consumer needs a clock signalCLK. After the time T1, the clock provider may provide the clock signalCLK to the clock consumer.

At a time T2, the clock provider transmits the clock acknowledgementsignal ACK having the second logic value to the clock consumer. Thisindicates that the clock signal CLK is being stably provided to theclock consumer by the clock provider (see section I).

At a time T3, the clock request signal REQ transits to the first logicvalue. This may indicate that the clock consumer informs the clockprovider that the clock signal CLK is no longer needed. After the timeT3, the clock provider may stop providing the clock signal CLK to theclock consumer or may still continue to provide the clock signal CLK.

At a time T4, the clock provider may transmit the clock acknowledgementsignal ACK having the first logic value to the clock consumer. Thisindicates that the clock provider cannot inform the clock consumer aboutthe provision of the clock signal CLK.

That is, in FIG. 5A, a section in which the stable provision of theclock signal CLK to the clock consumer by the clock provider isguaranteed is only the section I. In the other section II, it cannot beknown whether the clock signal CLK is being provided to the clockconsumer by the clock provider.

In FIG. 5B, in a case where the second logic value is expressed as ‘1’and the first logic value is expressed as ‘0,’ possible combinations ofthe clock request signal REQ and the clock acknowledgement signal ACKand possible transitions between them are illustrated.

Referring to FIG. 5B together with FIG. 5A, a state S0 is before thetime T1 and after the time T4, and a state S1 is from the time T1 to thetime T2. In addition, a state S2 is from the time T2 to the time T3, anda state S3 is from the time T3 to the time T4. A combination of valuesof the clock request signal REQ and the clock acknowledgement signal ACKchanges sequentially from the state S0 to the state S1, the state S2,the state S3 and then to the state S0 (see solid arrows).

If a circuit is implemented such that the clock request signal REQ andthe clock acknowledgement signal ACK simultaneously transit to thesecond logic value at the time T1, the combination of the values of theclock request signal REQ and the clock acknowledgement signal ACK mayswitch from the state S0 directly to the state S2. Similarly, if thecircuit is implemented such that the clock request signal REQ and theclock acknowledgement signal ACK simultaneously transit to the firstlogic value at the time T3, the combination of the values of the clockrequest signal REQ and the clock acknowledgement signal ACK may switchfrom the state S2 directly to the state S0 (see dotted arrows).

The full handshake method will now be described with reference to FIGS.1, 2 and 4 again.

According to the full handshake method, when the first IP block 200needs a clock signal, it activates the first clock request signal REQ1.For example, the first IP block 200 sets the first clock request signalREQ1 to a high state.

The CMU 100 activates the first clock acknowledgement signal ACK1 forthe first clock request signal REQ1 in response to the activation of thefirst clock request signal REQ1. That is, the CMU 100 sets the firstclock acknowledgement signal ACK1 to a high state.

The CMU 100 may transmit the first clock signal CLK1 to the first IPblock 200 before the activation of the first clock acknowledgementsignal ACK1. Alternatively, the CMU 100 may transmit the first clocksignal CLK1 to the first IP block 200 at the same time as the activationof the first clock acknowledgement signal ACK1.

When the first IP block 200 does not need a clock signal, the firstclock request signal REQ1 is deactivated. That is, the first IP block200 sets the first clock request signal REQ1 to a low state.

When the first clock request signal REQ1 is in the low state, the CMU100 sets the first clock acknowledgement signal ACK1 to a low state. Atthe same time, the CMU 100 may deactivate the first clock signal CLK1.

The first IP block 200 may operate normally while the first clockacknowledgement signal ACK1 is active. For example, the first IP block200 may operate normally while the first clock acknowledgement ACK1 isin a high state. The first IP block 200 may switch to a sleep mode whenit senses that the first clock acknowledgment signal ACK1 has reachedthe low state.

The full handshake method of the CMU 100 according to exemplaryembodiments of the inventive concept will now be described withreference to FIGS. 1 and 2. The full handshake method will be describedbased on the assumption that the clock components 120 a through 120 f ofFIG. 2 are a PLL controller, a clock MUX unit, a first clock dividingunit, a shortstop unit, a second clock dividing unit and a first clockgating unit, respectively. However, this is merely an example in whichthe inventive concept can be implemented, and the scope of the presentdisclosure is not limited to this example. In an embodiment, the PLLcontroller disables the PLL in response to a request signal from a childclock component, and then relies on the OSC. In an embodiment, theshortstop unit includes a shortstop circuit that is configured totemporarily stop a clock signal for a period of time. For example, theshortstop circuit maintains pulses of the clock signal during a firstperiod, sets the clock signal to a constant low during a second period(e.g., disables the pulses), and restores the pulse of the clock signalduring a third period.

The PLL controller, the clock MUX unit, the first clock dividing unit,the shortstop unit, the second clock dividing unit and the first clockgating unit may include the clock sources 124 a through 124 f,respectively.

Specifically, the PLL controller may include a clock MUX circuit whichreceives signals from the oscillator OSC and the PLL. The clock MUX unitmay include a clock MUX circuit which receives a plurality of clocksignals. The first clock dividing unit may include a first clockdividing circuit. The shortstop circuit may include a first clock gatingcircuit. The second clock dividing unit may include a second clockdividing circuit. The first clock gating unit may include a second clockgating circuit.

In addition, the PLL controller may include the clock control circuit122 a. The clock MUX unit may include the clock control circuit 122 b.The first clock dividing unit may include the clock control circuit 122c. The shortstop circuit may include the clock control circuit 122 d.The second clock dividing unit may include the clock control circuit 122e. The first clock gating unit may include the clock control circuit 122f.

Each of the clock control circuits 122 a through 122 f may communicateaccording to the full handshake method. For example, each of the clockcontrol circuits 122 a and 122 b may support the full handshake methodbetween the PLL controller and the clock MUX unit.

Each of the clock control circuits 122 b and 122 c may support the fullhandshake method between the clock MUX unit and the first clock dividingunit.

Each of the clock control circuits 122 c and 122 d may support the fullhandshake method between the first clock dividing unit and the shortstopcircuit.

Each of the clock control circuits 122 d and 122 e may support the fullhandshake method between the shortstop circuit and the second clockdividing unit.

Each of the clock control circuits 122 e and 122 f may support the fullhandshake method between the second clock dividing unit and the firstclock gating unit.

Likewise, each of the clock control circuit 122 f and the channelmanagement circuit 130 may support the full handshake method between thefirst clock gating unit and the channel management unit 130.

The first IP block 200 may request the CMU 100 to provide an operationclock signal according to the full handshake method. For example, whenthe first IP block 200 needs an operation clock signal, it may activatea clock request signal. That is, when the first IP block 200 needs anoperation clock signal, it may transmit the activated clock requestsignal to the CMU 100.

The channel management circuit 130 receives the activated clock requestsignal.

The channel management circuit 130 transmits the activated clock requestsignal to the first clock gating unit (e.g., clock component 120 f). Thefirst clock gating unit transmits the activated clock request signal tothe second clock dividing unit (e.g., clock component 120 e). The secondclock dividing unit transmits the activated clock request signal to theshortstop circuit (e.g., clock component 120 d). The shortstop circuittransmits the activated clock request signal to the first clock dividingunit (e.g., clock component 120 c). The first clock dividing unittransmits the activated clock request signal to the clock MUX unit(e.g., clock component 120 b). The clock MUX unit transmits theactivated clock request signal to the PLL controller (e.g., clockcomponent 120 a).

In an exemplary embodiment, each of the PLL controller, the clock MUXunit, the first clock dividing unit, the shortstop unit, the secondclock dividing unit, the first clock gating unit and the first channelmanagement circuit 130 is implemented as a combinational circuit.Therefore, the activated clock request signal may be transmitted at atime to the first channel management circuit 130 through the PLLcontroller.

The PLL controller activates a clock acknowledgement signal for theactivated clock request signal. That is, the PLL controller transmitsthe activated clock acknowledgement signal in response to the activatedclock request signal to the clock MUX unit. At the same time, the PLLcontroller transmits a clock signal CLK to the clock MUX unit. Forexample, the PLL controller may transmit the clock signal CLK to theclock MUX unit at the same time it transmits the activated clockacknowledgement signal.

The clock MUX unit transmits the activated clock acknowledgement signalto the first clock dividing unit. At the same time, the clock MUX unittransmits the clock signal CLK to the first clock dividing unit. Forexample, the clock MUX unit may transmit the clock signal CLK to thefirst clock dividing unit at the same time it transmits the activatedclock acknowledgement signal.

The first clock dividing unit transmits the activated clockacknowledgement signal to the shortstop circuit. At the same time, thefirst clock dividing unit transmits the clock signal CLK to theshortstop circuit. For example, the first clock dividing unit maytransmit the clock signal CLK to the shortstop circuit at the same timeit transmits the activated clock acknowledgement signal.

The shortstop unit transmits the activated clock acknowledgement signalto the second clock dividing unit. At the same time, the shortstop unittransmits the clock signal CLK to the second clock dividing unit. Forexample, the shortstop unit may transmit the clock signal CLK to thesecond clock dividing unit at the same time it transmits the activatedclock acknowledgement signal.

The second clock dividing unit transmits the activated clockacknowledgement signal to the first clock gating unit. At the same time,the second clock dividing unit transmits the clock signal CLK to thefirst clock gating unit. For example, the second clock dividing unit maytransmit the clock signal CLK to the second clock dividing unit at thesame time it transmits the activated clock acknowledgement signal.

The first clock gating unit transmits the activated clockacknowledgement signal to the first channel management circuit 130. Atthe same time, the first clock gating unit provides the clock signal CLKto the first IP block 200. For example, the first clock gating unit maytransmit the clock signal CLK to the first channel management circuit130 at the same time it transmits the activated clock acknowledgementsignal.

In the current embodiment, the clock acknowledgement signal may betransmitted at a time to the PLL controller through the first channelmanagement circuit 130.

When the first IP block 200 does not need a clock signal, it maydeactivate the clock request signal. That is, when the first IP block200 does not need a clock signal, it may transmit the deactivated clockrequest signal to the CMU 100.

The channel management circuit 130 receives the deactivated clockrequest signal. The channel management circuit 130 may transmit thedeactivated clock request signal to the first clock gating unit. Thefirst clock gating unit transmits the deactivated clock request signalto the second clock dividing unit. The second clock dividing unittransmits the deactivated clock request signal to the shortstop circuit.The shortstop circuit may transmit the deactivated clock request signalto the first clock dividing unit. The first clock dividing unit maytransmit the deactivated clock request signal to the clock MUX unit. Theclock MUX unit may transmit the deactivated clock request signal to thePLL controller.

Each of the PLL controller, the clock MUX unit, the first clock dividingunit, the shortstop unit, the second clock dividing unit, the firstclock gating unit and the first channel management circuit 130 may beimplemented as a combinational circuit. Therefore, the deactivated clockrequest signal may be transmitted at a time to the channel managementcircuit 130 through the PLL controller.

The PLL controller deactivates the clock acknowledgement signal inresponse to the deactivated clock request signal. That is, the PLLcontroller may transmit the deactivated clock acknowledgement signal tothe clock MUX unit. At the same time, the PLL controller may deactivatethe clock signal CLK or may still continue to transmit the clock signalCLK to the clock MUX unit.

The clock MUX unit transmits the deactivated clock acknowledgementsignal to the first clock dividing unit. At the same time, the clock MUXunit may transmit the deactivated the clock signal CLK or may stilltransmit the clock signal CLK to the first clock dividing unit.

The first clock dividing unit transmits the deactivated clockacknowledgement signal to the shortstop circuit. At the same time, thefirst clock dividing unit may deactivate the clock signal CLK or maystill transmit the clock signal CLK to the shortstop unit.

The shortstop circuit transmits the deactivated clock acknowledgementsignal to the second clock dividing unit. At the same time, theshortstop circuit may deactivate the clock signal CLK or may stilltransmit the clock signal CLK to the second clock dividing unit.

The second clock dividing unit transmits the deactivated clockacknowledgement signal to the first clock gating unit. At the same time,the second clock dividing unit may deactivate the clock signal CLK ormay still transmit the clock signal CLK to the first clock gating unit.

The first clock gating unit transmits the deactivated clockacknowledgement signal to the channel management circuit 130. At thesame time, the first clock gating unit deactivates the clock signal CLK.

Likewise, the clock acknowledgement signal may be transmitted at a timeto the PLL controller through the first channel management circuit 130.

Various types of clock components included in a semiconductor deviceaccording to embodiments will now be described.

FIG. 6 illustrates the implementation of a clock gating componentincluded in a semiconductor device according to an exemplary embodimentof the present inventive concept. FIG. 7 illustrates the structure ofthe clock gating component included in a semiconductor device accordingto an exemplary embodiment of the present inventive concept. FIG. 8 is atiming diagram illustrating the behavior of the clock gating componentincluded in a semiconductor device according to an embodiment of thepresent disclosure. The clock component 120 f or clock component 120 gmay be implemented by the clock gate component of FIG. 6 or FIG. 7.

Referring to FIG. 6, the clock gating component included in asemiconductor device according to an embodiment of the presentdisclosure includes a finite state machine (FSM) and a clock gating cellSEC_AP_RTL_CLKGATE. Here, the FSM refers to a calculation model ormachine composed of a finite number of states and the conversion betweenthe states. The FSM and/or the clock gating cell SEC_AP_RTL_CLKGATE maybe implemented using one or more logic gates. In an embodiment, theclock control circuit 122 f or clock control circuit 122 g isimplemented by the FSM, and the clock source 124 f or clock source 124 gis implemented by the clock gating cell SEC_AP_RTL_CLKGATE. The FSM andthe clock gating cell SEC_AP_RTL_CLKGATE of FIG. 6 correspond to anadapter and a core clock gating SEC_AP_RTL_CLKGATE of FIG. 7,respectively. Here, the FSM or the adapter may be operated by areference clock signal CLK_RF which belongs to a different clock domainfrom a clock signal CLK generated by a clock component and perform afull handshake with the clock gating cell SEC_AP_RTL_CLKGATE.

The FSM may receive a clock request signal CHILD_CLK_REQ from a childclock component and transmit a clock request signal PARENT_CLK_REQ to aparent clock component or output an enable signal EN for controlling theclock gating cell SEC_AP_RTL_CLKGATE according to the state of the FSM.For example, based on the state of the clock request signalCHILD_CLK_REQ and a corresponding acknowledgement it receives inresponse to sending the parent clock request signal PARENT_CLK_REQ, theFSM may determine it is time to activate a clock source (e.g., the clockgating cell SEC_AP_RTL_CLKGATE), and accordingly outputs the enablesignal EN to cause the clock source to output a clock signal CLK_OUTbased on an input clock signal CLK_IN. The clock gating cellSEC_AP_RTL_CLKGATE sends an enable feedback signal EN_FB to the FSM inresponse to the received enable signal EN or after it has begunoutputting the clock signal CLK_OUT in response to the received enablesignal.

The clock gating cell SEC_AP_RTL_CLKGATE receives a clock signal CLK_INaccording to the enable signal EN output from the FSM and outputs aclock signal CLK_OUT obtained by gating or bypassing the clock signalCLK_IN.

Referring also to FIG. 8, the FSM of the clock gating component mayinclude the following states.

A first state a1 is a state in which the clock gating component providesa clock signal CLK to a child clock component without performing a clockgating operation according to a clock request signal CHILD_CLK_REQhaving the second logic value received from the child clock component.It is assumed that the clock request signal CHILD_CLK_REQ received fromthe child clock component later transits to the first logic value.

A second state a2 is a state in which the clock gating componentperforms the clock gating operation. Accordingly, after a localhandshake latency period required for the clock gating operation of theclock gating component, the clock gating component transmits a clockacknowledgement signal CHILD_CLK_ACK having the first logic value to thechild clock component. In addition, the clock gating component transmitsa clock request signal PARENT_CLK_REQ having the first logic value to aparent clock component.

In a third state a3, the clock gating component requests the parentclock component to stop providing a clock by transmitting the clockrequest signal PARENT_CLK_REQ having the first logic value to the parentclock component. In a fourth state a4, the clock gating component waitsuntil it receives a clock acknowledgement signal PARENT_CLK_ACK havingthe first logic value from the parent clock component. This indicatesthat since the gating operation of the clock gating component has beencompleted, the clock gating operation of the parent component can beperformed, if necessary.

After the clock acknowledgement signal PARENT_CLK_ACK having the firstlogic value is received from the parent clock component, the provisionof a clock to the child clock component of the clock gating component iscompletely stopped in a fifth state a5.

Here, when receiving the clock request signal CHILD_CLK_REQ having thesecond logic value from the child clock component, the clock gatingcomponent transmits the clock request signal PARENT_CLK_REQ having thesecond logic value to the parent clock component and then stops theclock gating operation in a sixth state a6.

After a local handshake latency period required to stop the clock gatingoperation, if the clock gating component receives the clockacknowledgement signal PARENT_CLK_ACK having the second logic value fromthe parent clock component, it switches to a seventh state a7. Here, theseventh state a7 is the same as the first state a1.

The clock gating cell SEC_AP_RTL_CLKGATE includes a first logic circuitSYNC and a second logic circuit PREICG. The first logic circuit SYNCprovides the enable feedback signal EN_FB to the FSM in response toreceipt of the enable signal EN and provides a synchronous enable signalSYNC_EN to the second logic circuit PREICG based on the input clocksignal CLK_IN after receiving the enable signal EN. The second logiccircuit PREICG outputs the output clock output signal CLK_OUT based onthe input clock signal CLK_IN in response to the synchronous enablesignal SYNC_EN. The second logic circuit PREICG may be used to ensurethat a stable clock signal is output.

FIG. 9A illustrates the implementation of a clock MUX component includedin a semiconductor device according to an exemplary embodiment of thepresent inventive concept. In an embodiment, the clock component 120 bis implemented by the circuit of FIG. 9A. FIG. 9B illustrates an FSM ofthe clock MUX component included in a semiconductor device according toan exemplary embodiment of the present inventive concept. FIG. 10illustrates the structure of the clock MUX component included in asemiconductor device according to an exemplary embodiment of the presentinventive concept. FIGS. 11 through 20 are timing diagrams illustratingthe behavior of the clock MUX component included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept.

Referring to FIG. 9A, the clock MUX component included in asemiconductor device according to an exemplary embodiment of the presentinventive concept includes an FSM and a MUX circuit SEC_AP_RTL_GFMUX.The MUX circuit SEC_AP_RTL_GFMUX includes first and second logiccircuits SEC_AP_RTL_CLKGATE for receiving first and second clock signalsCLK0 and CLK1, and a multiplexer MUX, which may provide a STATUS signalto the FSM indicating whether it is currently outputting one of theclock signals or it has receiving an output select signal SEL_OUT fromthe FSM. The FSM receives a clock request signal CHILD_CLK_REQ throughan adaptor gate Adapter_CLKGATE (e.g., a logic circuit) from a childclock component and transmits clock request signals PARENT_CLK_REQ0 andPARENT_CLK_REQ1 to parent clock components. For example, the firstparent clock request signal PARENT_CLK_REQ0 may be transmitted to clockcomponent 120 a and the second parent clock request signalPARENT_CLK_REQ1 may be transmitted to an external clock component.

Here, the clock MUX component may include a glitch-free MUX. A glitchrefers to a temporary malfunction of a computer due to noise.

The FSM receives a select signal SEL. When the FSM determines that avalue of the select signal SEL has changed, the FSM compares the selectsignal SEL and a muxsel signal and determines whether these signals havethe same value.

When the select signal SEL and the muxsel signal do not have the samevalue, the FSM generates a detect change signal. Here, the detect changesignal may be generated by toggling a value of the detect change signalhaving a low state to a high state or by toggling the value of thedetect change signal having a high state to a low state.

The clock MUX component outputs a first clock signal CLK0 or a secondclock signal CLK1 as a clock signal CLK_OUT in response to the selectsignal SEL_OUT which is output from the FSM to the MUX. The child clockcomponent receives a clock output from the clock MUX component. Thefirst clock signal CLK0 may be output by clock component 120 a and thesecond clock signal CLK1 may be output by an external clock component.

Referring also to FIG. 9B, the FSM included in the clock MUX componentmay include the following states.

A first state b1 is a state in which clock gating is performed byhardware. This is a state in which both a parent clock component (of theclock MUX component) which stopped providing a clock to a child clockcomponent and a parent clock component (of the clock MUX component)which is still providing a clock signal exist. In this state, however,it is not guaranteed that all parent clock components of the clock MUXcomponent are in operation. That is, since the operation of unnecessaryparent clock components is stopped in this state, power consumption maybe at a minimum. Therefore, the clock MUX component cannot change itsselection according to the select signal SEL. Unlike the clock gatingcomponent, the clock MUX component can maintain an optimum state evenwhen receiving a clock request signal from a child clock component.

In a second state b2, all parent clock components of the clock MUXcomponent are woken up because the clock MUX component needs to changeits selection according to the select signal SEL.

A third state b3 is a state in which clock gating by the hardware is notperformed. That is, all parent clock components that were woken up areproviding clock signals to the clock MUX component. In this state, theclock MUX component can change its selection according to the selectsignal SEL.

In a fourth state b4, clock gating by the hardware is resumed after theclock MUX component changes its selection according to the select signalSEL. Therefore, the operation of parent clock components which do notneed a clock signal begins to be stopped in the fourth state b4. Thatis, in the fourth state b4, a clock stop request signal PARENT_CLK_REQis transmitted to the parent clock components which do not need theclock signal.

After receiving a clock acknowledgement signal PARENT_CLK_ACK from theparent clock components which do not need the clock signal, the clockMUX component returns to the first state b1. A fifth state b5illustrated in FIGS. 11 through 20 is the same as the first state b1.

Referring to FIG. 10, the clock MUX component included in asemiconductor device according to an exemplary embodiment of the presentinventive concept includes a gasket (e.g., a register), an arbiter(e.g., an arbitration circuit), a MUX converter, an adapter (e.g.,adaptor circuit), and a clock MUX. The gasket, the arbiter, the MUXconverter and the adapter perform signal transmission and receptionusing a reference clock signal CLK_RF, and the adapter controls theclock MUX according to the full handshake method.

The gasket may receive a request for selecting an input to the clock MUXthrough an S channel (S-CH). The request may include the muxsel signal.In this case, the muxsel signal may be encoded by a 4-phase synchronousfull handshake which is performed between the gasket and the arbiter,and transferred to the adapter.

Meanwhile, the arbiter also may receive a request for selecting an inputto the clock MUX through an H channel (H-CH). In this case, the arbiterreceives the request according to a 4-phase asynchronous full doublehandshake through the H channel (H-CH). The 4-phase asynchronous fulldouble handshake may include a lock request, a release request, a muxselsignal, which are input to the arbiter; and an acknowledgement which isoutput from the arbiter. In this case, the muxsel signal may be encodedby a 4-phase synchronous full handshake which is performed between thearbiter and the MUX converter, and transferred to the adapter.

The adapter includes an FSM, which is described with respect to FIGS. 9Aand 9B, and the muxsel signal may be decoded by 2-phase asynchronousfull handshake which is performed between the adapter and the clock MUX,and input to the clock MUX.

Referring to FIG. 11, a clock signal change occurs in a b3 sectionthrough the clock MUX component. Here, if a clock request signal of achild is in a low state and a clock acknowledgement signal for the childis in a low state between a b1 section and a b2 section, when a clockacknowledgement signal of a parent becomes a high state, the clockrequest signal of the child becomes a high state. In FIG. 11, clockrequest signals transmitted to all parents become a high state betweenthe b2 and b3 sections. However, a clock request signal in a high statecan also be transmitted only to a previous parent or a next parent. FIG.11 illustrates four parent clock requests PARENT_CLK_REQ_0,PARENT_CLK_REQ_1, PARENT_CLK_REQ_2, and PARENT_CLK_REQ_3 to show anexample of a clock MUX unit being capable of receiving four differentclock signals and communicating with four different parent clockcomponents providing these clock signals. However, embodiments of theclock MUX unit are not limited thereto as fewer or additional parentclock components may be supported in alternate embodiments.

Referring to FIG. 12, if a clock request signal of a child is in a lowstate and a clock acknowledgement signal for the child is in a low statebetween the b1 section and the b2 section, the clock request signal ofthe child becomes a high state before a clock acknowledgement signal ofa parent becomes a high state.

Referring to FIG. 13, between the b1 section and the b2 section, a clockrequest signal of a child is in a high state, and a clockacknowledgement signal for the child is in a low state.

Referring to FIG. 14, between the b1 section and the b2 section, a clockrequest signal of a child is in a high state, and a clockacknowledgement signal for the child is in a high state.

Referring to FIG. 15, between a b3 section and a b4 section, a clockrequest signal of a child is in a low state, a clock acknowledgementsignal for the child is in a low state, and the clock request signal ofthe child maintains the low state.

Referring to FIG. 16, between the b3 section and the b4 section, a clockrequest signal of a child is in a low state, a clock acknowledgementsignal for the child is in a low state, and the clock request signal ofthe child is toggled from the low state to a high state.

Referring to FIG. 17, between the b3 section and the b4 section, a clockrequest signal of a child is in a low state, a clock acknowledgementsignal for the child is in a high state, and the clock request signal ofthe child maintains the low state.

Referring to FIG. 18, between the b3 section and the b4 section, a clockrequest signal of a child is in a high state, a clock acknowledgementsignal for the child is in a low state, and the clock request signal ofthe child maintains the high state.

Referring to FIG. 19, between the b3 section and the b4 section, a clockrequest signal of a child is in a high state, a clock acknowledgementsignal for the child is in a high state, and the clock request signal ofthe child is toggled from the high state to a low state.

Referring to FIG. 20, between the b3 section and the b4 section, a clockrequest signal of a child is in a high state, a clock acknowledgementsignal for the child is in a high state, and the clock request signal ofthe child maintains the high state.

FIG. 21A illustrates the implementation of a clock dividing componentincluded in a semiconductor device according to an exemplary embodimentof the present inventive concept. The clock component 120 c or clockcomponent 120 e may be implemented by the clock dividing component ofFIG. 21A. FIG. 21B illustrates an FSM of the clock dividing componentincluded in a semiconductor device according to an exemplary embodimentof the present inventive concept. FIG. 22 illustrates the structure ofthe clock dividing component included in a semiconductor deviceaccording to an exemplary embodiment of the present inventive concept.FIG. 23 is a timing diagram illustrating the behavior of the clockdividing component included in a semiconductor device according to anembodiment of the present disclosure.

Referring to FIG. 21A, the clock dividing component included in asemiconductor device according to an embodiment of the present inventiveconcept includes an adapter Adapter_CLKGATE (e.g., a logic gate), anFSM, and a clock dividing circuit SEC_AP_RTL_CLKDIV_SKEWLESS. Theadapter Adapter_CLKGATE receives a clock request signal CHILD_CLK_REQfrom a child clock component and transmits a clock request signalPARENT_CLK_REQ to a parent clock component. The adapter Adapter_CLKGATEmay also receive a merged clock request CLKGATE_CLK_REQ that is amerging of the CHILD_CLK_REQ and an additional clock request FSM_CLK_REQfrom the FSM. The merged clock request CLKGATE_CLK_REQ may be generatedby performing an OR operation on the CHILD_CLK_REQ and the FSM_CLK_REQ.The FSM determines a clock dividing ratio DIVRATIO and provides thedetermined clock dividing ratio DIVRATIO to the adapter Adapter_CLKGATE.The FSM may control the clock dividing circuit according to the fullhandshake method. For example, the Adapter_CLKGATE (e.g., one or morelogic circuits) may send a stop request signal STOPREQ to the clockdividing circuit SEC_AP_RTL_CLKDIV_SKEWLESS. In an embodiment, the clockdividing circuit SEC_AP_RTL_CLKDIV_SKEWLESS performs a dividingoperation on an input clock signal CLK_IN using the clock dividing ratioDIVRATIO to generate an output clock signal CLK_OUT after receiving theclock dividing ration DIVRATIO from the FSM and provides anacknowledgement signal to the FSM.

Referring also to FIG. 21B, the FSM included in the clock dividingcomponent may include the following states.

A first state c1 is a state in which clock gating is performed byhardware. This is a state in which both a parent clock component (of theclock dividing component) which stopped providing a clock signal to achild clock component and a parent clock component (of the clockdividing component) which is still providing a clock signal can exist.In this state, however, it is not guaranteed that all parent clockcomponents of the clock dividing component are in operation. That is,since the operation of unnecessary parent clock components is stopped inthis state, power consumption may be at a minimum. Therefore, the clockdividing component cannot change the clock dividing ratio DIVRATIO. Forexample, in state cl, even though a request for change of the dividingratio DIVCHG_REQ is input, the clock dividing component cannot changethe clock dividing ratio DIVRATIO.

In a second state c2, all parent clock components of the clock dividingcomponent are woken up because the clock dividing component needs tochange the clock dividing ratio DIVRATIO. The waking up of the parentclock components may be caused by outputting a clock request CLK_REQ tothe parent clock components.

A third state c3 is a state in which clock gating by the hardware is notperformed. That is, all parent clock components that were woken up areproviding clock signals to the clock dividing component. In this state,the clock dividing component can change the clock dividing ratio. Forexample, a clock dividing ratio change request CLKDIV_DIVCHG_REQ may beoutput to cause the change. After the change, and after receipt of anInput synchronization_CLKDIV_DIVCHG_ACK, an acknowledgement of thechange DIVCHG_ACK is output.

In a fourth state c4, clock gating by the hardware is resumed after theclock dividing component changes the clock dividing ratio. Therefore,the operation of parent clock components which do not need a clocksignal begins to be stopped. That is, in the fourth state c4, a clockstop request signal PARENT_CLK_REQ is transmitted to the parent clockcomponents which do not need the clock signal.

After receiving a clock acknowledgement signal PARENT_CLK_ACK from theparent clock components which do not need the clock signal, the clockdividing component returns to the first state cl. A fifth state c5illustrated in FIG. 23 is the same as the first state c1.

Referring to FIG. 22, the clock dividing component included in asemiconductor device according to an embodiment of the presentdisclosure includes a gasket, an arbiter, and an adapter. The gasket,the arbiter, and the adapter perform signal transmission and receptionusing a reference clock signal CLK_RF, and the adapter controls a clockdivider according to the full handshake method.

The gasket may receive a request signal for changing clock dividingratios through an S channel (S-CH). The request may include theDIVRATIO, which is a divratio signal. In this case, the request signalmay be encoded by a synchronous full handshake which is performedbetween the gasket and the arbiter, and transferred to the adapter.

Meanwhile, the arbiter also may receive a request signal for changingclock dividing ratios through an H channel (H-CH). In this case, thearbiter receives the request signal according to a asynchronous fulldouble handshake through the H channel (H-CH). The 4-phase asynchronousfull double handshake may include a lock request, a release request, adivratio signal, which are input to the arbiter; and an acknowledgementwhich is output from the arbiter. In this case, the request signal maybe encoded by a synchronous full handshake which is performed betweenthe arbiter and the adapter, and transferred to the adapter.

The adapter includes an FSM, which is described with respect to FIGS.21A and 21B, and the request signal may be decoded by an asynchronousfull handshake which is performed between the adapter and the clockdivider, and input to the clock divider.

Referring to FIG. 23, a change in the clock dividing ratio DIVRATIOoccurs in a c3 section. The clock divider operates in response to aclock dividing ratio change request CLKDIV_DIVCHG_REQ transmitted to theclock divider.

FIG. 24 illustrates the implementation of a PLL controller included in asemiconductor device according to an exemplary embodiment of the presentinventive concept. FIG. 25 illustrates the structure of a multiplexerMERGE_MUXSEL of the PLL controller circuit included in a semiconductordevice according to an embodiment of the present disclosure. FIGS. 26and 27 are timing diagrams illustrating the behavior of the PLLcontroller included in a semiconductor device according to an exemplaryembodiment of the present inventive concept.

Referring to FIG. 24, the PLL controller included in a semiconductordevice according to an exemplary embodiment of the present inventiveconcept includes an adapter, a multiplexer, etc. The adapter serves as acontrol circuit which transmits a request signal and an acknowledgementsignal. The adapter may send and receive REQ/ACK to and from a parentclock component when the parent clock component exists, while theadapter may bypass when the parent clock component does not exist.

Referring to FIG. 25, the multiplexer MERGE_MUXSEL communicates with aspecial function register (SFR) and a system clock oscillator(SYSCLK_OSC) according to the full handshake method and outputs a selectsignal SEL.

In FIGS. 26 and 27, timing diagrams illustrating the operation of thePLL controller circuit are provided. In particular, FIG. 26 is a timingdiagram illustrating the operation of the multiplexer MERGE_MUXSEL, andFIG. 27 is a timing diagram illustrating the operation of TRANS_HCH2PH.

FIG. 28 illustrates the implementation of a PLL user controller includedin a semiconductor device according to an exemplary embodiment of thepresent inventive concept.

Referring to FIG. 28, the PLL user controller includes an adapter, amultiplexer, etc. The adapter serves as a control circuit whichtransmits a request signal and an acknowledgement signal. The adaptermay send and receive REQ/ACK to and from a parent clock component whenthe parent clock component is exists, while the adapter may bypass whenthe parent clock component does not exist.

FIG. 29 illustrates the implementation of an adapter component includedin a semiconductor device according to an exemplary embodiment of thepresent inventive concept.

Referring to FIG. 29, the adapter component merges a plurality ofrequest channels into one channel. The adapter component communicatesaccording to the full handshake method. The adapter component receives aclock request signal from a child and transmits the clock request signalto a parent. In addition, the adapter component receives a clockacknowledgement signal from the parent and transmits the clockacknowledgement signal to the child.

In FIG. 29, a path between CHILD_CLK_REQ and PARENT_CLK_REQ may beimplemented using only combinational cells. This path may be utilized tominimize cycle latency of a request path. In FIG. 29, a path betweenPARENT_CLK_ACK and CHILD_CLK_ACK may be implemented using onlycombinational cells. This path may be utilized to minimize cycle latencyof an acknowledge path. In FIG. 29, a path from CHILD_CLK_REQ toCHILD_CLK_ACK may be implemented using only combinational cells. Thispath may be utilized to minimize cycle latency of arequest-to-acknowledge path. In FIG. 29, a path from PARENT_CLK_ACK toPARENT_CLK_REQ may be implemented using only combinational cells. Thispath may be utilized to minimize cycle latency of anacknowledge-to-request path. Some of the four paths mentioned above maybe intentionally separated by a sequential cell in order to prevent acombinational loop.

FIG. 30 illustrates the structure of a hysteresis filter included in asemiconductor device according to an exemplary embodiment of the presentinventive concept. The adaptor hysteresis filterADAPTER_HYSTERESISFILTER of FIG. 24 may be implemented by the hysteresisfilter of FIG. 30. FIGS. 31 through 33 are timing diagrams illustratingthe behavior of the hysteresis filter included in a semiconductor deviceaccording to an embodiment of the present disclosure.

Referring to FIG. 30, the hysteresis filter is included in an adapter.Referring to FIGS. 31 through 33, the hysteresis filter generates arequest signal filtered using a counter.

FIG. 34 is a block diagram of an embodiment of the PMU 300 illustratedin FIG. 1 according to an exemplary embodiment of the present inventiveconcept. FIGS. 35 through 39 are timing diagrams illustrating examplesof a clock on/off operation of the PMU 150.

Referring to FIG. 34, the PMU 300 may communicate with a CMU 100 througha CMU interface circuit (CMU I/F) 151 according to the full handshakemethod. In addition, the PMU 300 may further include a power sequencemanagement circuit 152 and a scan dump sequence management circuit 153.

FIG. 35 illustrates the operation of the PMU 300 in a booting sequence,FIG. 36 illustrates the operation of the PMU 300 in a power-downsequence for w/retention of the CMU 100, FIG. 37 illustrates theoperation of the PMU 300 in a power-up sequence for w/retention of theCMU 100, FIG. 38 illustrates the operation of the PMU 300 in apower-down sequence for w/o retention of the CMU 100, and FIG. 39illustrates the operation of the PMU 300 in a power-up sequence for w/oretention of the CMU 100.

Referring to FIG. 35, in a power-up state following the bootingsequence, a PLL operates. After the operation of the PLL, clock gatingby hardware according to various embodiments is performed, if necessary,in an environment for minimizing unnecessary power consumption.

Referring to FIG. 36 and FIG. 1, the power-down sequence is as follows.

First, a bus transaction between the CMU 100 and IP blocks 200 through220 is terminated, and the provision of clock signals CLK1 through CLK3by the CMU 100 is stopped. Then, the use of the PLL is stopped byswitching use of the PLL to an oscillator, and the CMU 100 obtains thecontrol over a clock source on which clock gating by the hardware hasnot been performed. After a retention operation, the oscillator isstopped. The CMU 100 may temporarily generate clock signals for theretention operation.

Referring to FIG. 37, the power-up sequence is as follows.

First, the oscillator is operated to perform a retention operation. Forthe retention operation, the CMU 100 may temporarily generate a clocksignal. Next, the control over the clock source on which clock gating bythe hardware has not been performed is removed, and the PLL is operated.Then, the bus transaction between the CMU 100 and the IP blocks 200through 220 is prepared to be performed. Accordingly, the power-upsequence is completed.

Referring to FIG. 38, the power-down sequence is as follows.

First, the bus transaction between the CMU 100 and the IP blocks 200through 220 is terminated, and the provision of clock signals by the CMU100 is stopped. Next, the use of the PLL is stopped by switching fromuse of the PLL to use of the oscillator, and the CMU 100 obtains thecontrol over the clock source on which clock gating by hardware has notbeen performed. Then, the oscillator is stopped.

Referring to FIG. 39, the power-up sequence is as follows.

First, the oscillator is operated, the control over the clock source onwhich clock gating by the hardware has not been performed is removed,and the PLL is operated. Then, the bus transaction between the CMU 100and the IP blocks 200 through 220 is prepared to be performed.Accordingly, the power-up sequence is completed.

FIG. 40 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept.

Referring to FIG. 40, the semiconductor device 700 includes a centralprocessing unit (CPU) 710, a clock generator 720, a CMU 730, a randomaccess memory (RAM) 740, a read only memory (ROM) 750, and a memorycontrol unit 760. An oscillator OSC may be provided outside thesemiconductor device 700 to provide an oscillation signal. The CMU 730may be replaced with the CMU 100 of FIG. 1. However, this is merely anembodiment, and the semiconductor device 700 according to theembodiments can include various other functional blocks. In addition,the oscillator OSC can also be included in the semiconductor device 700.The semiconductor device 700 of FIG. 40 may be included in asemiconductor system as an application processor.

The clock generator 720 generates a reference clock signal CLK_IN havinga reference frequency using a signal from the oscillator OSC. The CMU730 may receive the reference clock signal CLK_IN, generate an operationclock signal CLK_OUT having a certain frequency, and provide theoperation clock signal CLK_OUT to each functional block. The CMU 730 mayinclude one or more master clock controllers and one or more slave clockcontrollers. Each of the clock controllers may generate the operationclock signal CLK_OUT using the reference clock signal CLK_IN.

In addition, since the clock controllers included in the CMU 730 areconnected by channels, the management of clock signals can be performedhardware-wise. Also, since the clock controllers included in the CMU 730are connected to the functional blocks by channels, a clock request andan acknowledgement can be performed hardware-wise.

The CPU 710 may process or execute codes and/or data stored in the RAM740. For example, the CPU 710 may process or execute the codes and/orthe data in response to an operation clock signal output from the CMU730. The CPU 710 may be implemented as a multi-core processor. Themulti-core processor is one computing component having two or moreindependent and substantial processors, and each of the processors mayread and execute program instructions. Since the multi-core processorcan simultaneously run a plurality of accelerators, a data processingsystem including the multi-core processor can performmulti-acceleration.

The RAM 740 may temporarily store program codes, data, or instructions.For example, program codes and/or data stored in an internal or externalmemory (not illustrated) may be temporarily stored in the RAM 740 underthe control of the CPU 710 or according to booting code stored in theROM 750. The memory control module 760 is a block for interfacing withthe internal or external memory. The memory control module 760 controlsthe overall operation of the memory and controls data exchange between ahost and the memory.

While the present inventive concept has been particularly shown anddescribed with reference to exemplary embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes inform and detail may be made therein without departing from the spiritand scope of the present inventive concept.

What is claimed is:
 1. A system on chip (SoC) comprising: a plurality ofintellectual property (IP) blocks; and a clock management unit (CMU)performing clock gating on at least one of the IP blocks, one of the IPblocks providing a request signal to the CMU indicating the one of theIP blocks desires to enter a selected one of a sleep mode and an activemode, wherein the CMU outputs a clock signal and an acknowledgementsignal (Ack) to the one of the IP blocks in response to the requestsignal indicating the one of the IP blocks desires to enter the activemode, and activates the Ack signal upon determining the output clocksignal is stable.
 2. The SoC of claim 1, wherein the CMU deactivates theacknowledgement signal to indicate the CMU has stopped outputting theoutput clock signal in response to the request signal indicating the oneof the IP blocks desires to enter the sleep mode, and then stopsproviding the output clock signal to the one of the IP blocks.
 3. TheSoC of claim 1, further comprising a power management unit cutting offpower to the CMU when no request signals have been sent by the IP blocksduring a given period.
 4. The SoC of claim 1, wherein the CMU comprisesa controller receiving a first signal from a crystal oscillator and asecond signal from a phase locked loop (PLL), and providing one of thereceived signals as the output clock signal and the acknowledgementsignal in response to the request signal.
 5. The SoC of claim 1, whereinthe CMU comprises: a multiplexer receiving an internal clock signal andan external clock signal, and providing one of the received clocksignals as the output clock signal; and a controller providing theacknowledgement signal in response to the request signal.
 6. The SoC ofclaim 1, wherein the CMU comprises: a frequency dividing circuitdividing an input clock signal to generate a divided clock signal, andproviding the divided clock signal as the output clock signal; and acontroller providing the acknowledgement signal in response to therequest signal.
 7. The SoC of claim 1, wherein the CMU comprises: ashortstop circuit performing an operation on an input clock signal togenerate a resulting clock signal comprising a plurality of pulsesduring a first period and a constant level during a second period, andproviding the resulting clock signal as the output clock signal; and acontroller providing the acknowledgement signal in response to therequest signal.
 8. The SoC of claim 1, wherein the CMU comprises: acontrol circuit outputting a control signal and the acknowledgementsignal in response to the request signal; and a clock source outputtingthe clock signal in response to the control signal.
 9. The SoC of claim1, wherein the CMU comprises: a first clock component providing a firstrequest signal indicating a first one of the IP blocks desires to enterone of a sleep mode and an active mode; a second clock componentproviding a second request signal indicating a second one of the IPblocks desires to enter one of a sleep mode and an active mode; and athird clock component to start providing a clock signal to both thefirst and second clock components when one of the request signalsindicate a desire to enter the active mode, and stop providing the clocksignal when both of the request signals indicate a desire to enter thesleep mode.
 10. The SoC of claim 1, wherein the CMU comprises: a clockcomponent performing the clock gating; a channel management (CM) circuitmanaging a channel connecting the CM circuit to the one IP block; and awire connecting the clock component to the CM circuit, wherein therequest signal is sent across the wire from the CM circuit to the clockcomponent, and wherein the Ack signal is sent across the wire from theclock component to the CM circuit.
 11. The SoC of claim 1, wherein theone of the IP blocks enters the selected mode in response to theacknowledgement signal.
 12. A clock management unit (CMU) comprising: acontroller circuit configured to output a first clock signal based on anoutput from a phase locked loop or an oscillator; a multiplexing circuitconfigured to output one of the first clock signal and a second clocksignal; a first clock dividing circuit configured to perform a firstdividing operation on an output of the multiplexing circuit to generatea third clock signal; a shortstop circuit configured to selectively stoppulses of the third clock signal to generate a fourth clock signal; asecond clock dividing circuit configured to perform a second dividingoperation on an output of the shortstop circuit to generate a fifthclock signal; and a first clock gating circuit configured to selectivelyoutput the fifth clock signal.
 13. The CMU of claim 12, furthercomprising: a second clock gating circuit configured to selectivelyoutput the fifth clock signal, wherein the second clock dividing circuitprevents output of the fifth clock signal to the first clock gatingcircuit when a request is received from both clock gating circuitsindicating that provision of a clock signal is to be stopped.
 14. TheCMU of claim 13, wherein each of the circuits communicates with anadjacent one of the circuits using full handshaking.
 15. The CMU ofclaim 14, wherein the full handshaking comprises a child circuit amongthe circuits outputting a request to a parent circuit among the circuitsand the parent circuit outputting an acknowledgement to the childcircuit indicating that the request was received.
 16. The CMU of claim15, wherein the request indicates that provision of a clock signal is tobe started or stopped.
 17. The CMU of claim 12, further comprising: achannel management (CM) circuit configured to interface the first clockgating circuit with an intellectual property (IP) block, wherein thefirst clock gating circuit is configured to output the fifth clocksignal to the IP block.
 18. The CMU of claim 12, wherein the secondclock signal is provided by a source located external to the CMU.